Previous GATE Questions on Shift Registers with Solutions (1987 - Till Date)

1992

4.       The initial contents of the 4 bit serial in serial out, right shift, shift register shown in figure, are 0110. After three clock pulses are applied, the contents of the shift register will be

                       

                        a.       0000

                        b.      0101

                        c.       1010

                        d.      1111

Answer:     C

Solution :    https://www.youtube.com/watch?v=0VtDZLpnhOM

1996

2.       A pulse train can be delayed by a finite number of clock periods using a

            a.       Serial In Serial Out shift register

            b.      Serial In Parallel Out shift register

            c.       Parallel In serial Out shift register

            d.      Parallel In parallel Out shift register

Answer:    A

               Solution :      

11.    A 4 bit shift register, which shifts 1 bit to the right at every clock pulse, is initialized to values 1000 for (Q₀Q₁Q₂Q₃). The D input is derived from Q₀, Q₂ and Q₃ through two XOR gates as shown in figure.

            a.       Write the 4 bit values (Q₀Q₁Q₂Q₃) after each clock pulse till the pattern (1000)             reappears on (Q₀Q₁Q₂Q₃).

            b.      To what values should the shift register be initialized so that the pattern (1001)            occurs after the first clock pulse?

                          Solution :       https://www.youtube.com/watch?v=w--ZTa4Udk0

1997

15.   Circuit shown in the figure is an NMOS shift register. All transistors are NMOS enhancement type with threshold voltage V_T = 1 volt. Supply used is V_DD = 5 volts.

Two non- overlapping clocks ø₁ and ø₂ are as shown in the figure is and have large pulse widths.

All capacitors are initially discharged and the V_in = 0 volts is applied. If values of capacitors are C₁ = 2 pF and C₂ = 1 pF. Find out voltage V_C2 on capacitor C₂ after ø₂ goes low. Neglect body effect on V_T in your evaluation.

                         Solution :     https://www.youtube.com/watch?v=fa7OqcOcap0 

2004

4.       Choose the correct one from among the alternatives A,B,C,D after matching an item from Group 1 with the most appropriate item in Group 2.

Group 1	Group 2
P: Shift Register	1: Frequency division
Q: Counter	2: Addressing in memory chips
R: Decoder	3: Serial to Parallel data conversion

            a.       P – 3, Q – 2, R – 1 

            b.      P – 3, Q – 1, R – 2

            c.       P – 2, Q – 1, R – 3

            d.      P – 1, Q – 2, R – 2

Answer:    B

                  Solution :  https://www.youtube.com/watch?v=2d-9lEnp3x8

2006

4.       For the circuit shown, two 4-bit parallel in serial out shift registers loaded with the data shown are used to fed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the outputs sum and carry of the full adder should be ……respectively.

            a.       0, 0

            b.      0, 1

            c.       1, 0

            d.      1, 1

Answer:    D

                Solution :     https://www.youtube.com/watch?v=8xaQJ8NM_p4