GATE 2023 - Important Concepts, Short cuts, Complete Solutions, Examples and Practice Problems: GATE 2007

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GATE 2007 ECE Network Theory - Complete Video Solutions with Answers

2007

1. An independent voltage source in series with an impedance Z_s = R_s + j X_s delivers a maximum average power to a load impedance Z_L when
a) Z_L = R_s + jX_s
b) Z_L = R_s
c) Z_L = jX_s
d) Z_L = R_s - jX_s

Solution: https://www.youtube.com/watch?v=o9Awvha9eAg

2. The RC circuit shown in the figure is a

a) Low Pass Filter
b) High Pass Filter
c) Band Pass Filter
d) Band Reject Filter

Solution: https://www.youtube.com/watch?v=0f9FRURijpw

3. Two series resonant filters are as shown in the figure. Let the 3-dB bandwidth of filter 1 is B₁ and that of Filter 2 is B₂. The value of B₁/B₂ is

a) 4
b) 1
c) 1/2
d) 1/4

Solution: https://www.youtube.com/watch?v=lMKem0ESd64

4. For the circuit shown in the figure, the Thevenin's voltage and resistance looking into X-Y are

a) 4/3 volts. 2 Ω
b) 4 volts. 2/3 Ω
c) 4/3 volts. 2/3 Ω
d) 4/ volts. 2 Ω

Solution: https://www.youtube.com/watch?v=M9_ZDSgAKLI

5. In the circuit shown, V_c is 0 volts at t = 0 sec. For t > 0, the capacitor current i_c(t), where t is in seconds, is given by

Solution: https://www.youtube.com/watch?v=U9lh2d-zwTg

6. In the AC network shown in the figure, the phasor voltage V_AB(in volts) is:

Solution: https://www.youtube.com/watch?v=CNz1YebFlDw

GATE 2007 ECE Control Systems - Complete Video Solutions with Answers

GATE 2007

1. If the closed loop transfer function of a control system is given as T(s) = (s – 5)/[(s + 2)(s + 3)], then it is

a) an unstable system

b) an uncontrollable system

c) a minimum phase system

d) a non-minimum phase system

Solution : https://www.youtube.com/watch?v=4soEmuGvfcI

2. If the Laplace Transform of a signal y(t) is Y(s) = 1/[s(s – 1)], then its final value is:

a) – 1

b) 0

c) 1

d) unbounded

Solution : https://www.youtube.com/watch?v=cvCDerivzj0

3. A control system with a PD controller is shown in the figure.

If the velocity error constant K_v = 1000 and the damping ratio ξ = 0.5, then the values of K_p and K_D are

a) K_p = 100, K_D = 0.09

b) K_p = 100, K_D = 0.9

c) K_p = 10, K_D = 0.09

d) K_p = 10, K_D = 0.9

Solution : https://www.youtube.com/watch?v=vxHx4zTs5vg

4. The transfer function of a plant is T(s) = 5/[(s + 5)(s² + s + 1)]. The second order approximation of T(s) using dominant pole concept is

Solution : https://www.youtube.com/watch?v=y1BxLLTHJOI

5. The open loop transfer function of a plant is given as G(s) = 1/(s² – 1). If the plant is operated in a unity feedback configuration, then the lead compensator that can stabilize this control system is

Solution : https://www.youtube.com/watch?v=HJ09FtxcO-I

6. A unity feedback control system has an open loop transfer function G(s) = – K/[s(s² + 7s + 12)]. The gain k for which s = –1+j1 will lie on the root locus of this system is

a) 4

b) 5.5

c) 6.5

d) 10

Solution : https://www.youtube.com/watch?v=ppJqQhOp_xk

7. The asymptotic Bode plot of a transfer function is as shown in figure. The transfer function G(s) corresponding to this Bode plot is

Solution : https://www.youtube.com/watch?v=fpM5ezwr90c

8. The state space representation of a separately excited DC servo motor dynamics is given as

where ω is the speed of the motor, i_a is the armature current and u is the armature voltage. The transfer function of the motor is

Solution : https://www.youtube.com/watch?v=jTt-sWQZS0Y

Statement for Linked Answer Questions 9 & 10:

9. The eigen value and eigen vector pairs (λ_i, v_i) for the system are

Solution :

10. The system matrix A is

Solution :

GATE 2007 ECE Video Solutions on Analog Circuits (Analog Electronics)

1. In a Transconductance amplifier, it is desirable to have
a. A large input resistance and a large output resistance
b. A large input resistance and a small output resistance
c. A small input resistance and a large output resistance
d. A small input resistance and a small output resistance

Solution: https://www.youtube.com/watch?v=XdHNm2Ly-Kc

2. For the OP-AMP circuit shown in the figure, V_o is

a. – 2 volts
b. – 1 volts
c. – 0.5 volts
d. + 0.5 volts

Solution: https://www.youtube.com/watch?v=GNXEesKW7VQ

3. In the OP-AMP circuit shown, assume that the diode current follows the equation I = I_Sexp(V/V_T). For V_i = 2 Volts, V_o = V₀₁, and for V_i = 4 Volts, V_o = V₀₂. The relationship between V₀₁ and V₀₂ is

a. V₀₂ = √2 V₀₁
b. V₀₂ = e² V₀₁
c. V₀₂ = V₀₁ ln2
d. V₀₂ - V₀₁= V_T ln2

Solution: https://www.youtube.com/watch?v=_FEUmzL53hg

Statement for Linked Answer Questions
Consider the OP-AMP circuit shown in the figure.

4. The Transfer function V_o(s)/ V_i(s) is

5. If V_i = V₁ sin(ωt) and V_o = V₂ sin(ωt+ø), then the minimum and maximum values of ø (in radians) are respectively
a. – π/2 and π/2
b. 0 and π/2
c. – π and 0
d. – π/2 and 0

Solution(4 & 5): https://www.youtube.com/watch?v=5BVus7UsCas

GATE 2007 ECE Video Solution on Digital Circuits (Digital Electronics)

1. X = 01110 and Y = 11001 are two 5 bit binary numbers represented in 2’s compliement format. The sum of X and Y represented in 2’s compliment format using 6 bits is
a. 100111
b. 001000
c. 000111
d. 101001

Solution : https://www.youtube.com/watch?v=BzttyDg5Psk

2. The Boolean function Y = AB + CD is to be realized using only 2 input NAND gates. The minimum number of gates required is
a. 2
b. 3
c. 4
d. 5

Solution : https://www.youtube.com/watch?v=NrSGprNRg7s

3. The following Boolean expression can be minimized to

Solution : https://www.youtube.com/watch?v=haH_7TtDohU

4. The circuit diagram of a standard TTL NOT gate is shown in the figure. When Vi = 2.5 volts, the modes of operation of the transistor will be

a. Q₁ reverse active, Q₂ normal active, Q₃ saturation and Q₄ cut-off
b. Q₁ reverse active, Q₂ saturation, Q₃ saturation and Q₄ cut-off
c. Q₁ normal active, Q₂ cut-off, Q₃ cut-off and Q₄ saturation
d. Q₁ saturation, Q₂ saturation, Q₃ saturation and Q₄ normal active

Solution : https://www.youtube.com/watch?v=rgKBuCdq0rw

5. In the following circuit X is given by

Solution : https://www.youtube.com/watch?v=pB5R0vNLQR0

6. In the following circuit, binary values were applied to the inputs X and Y inputs of the NAND latch shown in the figure in the sequence indicated below:
X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1;

The corresponding stable P, Q outputs will be

Solution : https://www.youtube.com/watch?v=PEBoEN_8dW8

7. For the circuit shown, the counter state (Q₁Q₀) follows the sequence

a. 00, 01, 10, 11, 00…..
b. 00, 01, 10, 00, 01…..
c. 00, 01, 11, 00, 01…..
d. 00, 10, 11, 00, 10…..

Solution : https://www.youtube.com/watch?v=aLGSUebXUW4

8. An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its three ports and the control register. The address lines A₀ to A₇ as well as the IO/M’ signal are used for address decoding. The range of addressees for which the 8255 chip would get selected is

a. F8H – FBH
b. F8H – FCH
c. F8H – FFH
d. F0H – F7H

Solution : https://www.youtube.com/watch?v=tWFKm8GgbEw

Statement for the linked answer questions 9 & 10 :
An 8085 assembly language program is given below.
Line 1 MVI A, B5H
2 MVI B, 0EH
3 XRI 69H
4 ADD B
5 ANI 9BH
6 CPI 9FH
7 STA 3010H
8 HLT

9. The contents of the accumulator just after execution of the ADD instruction in line 4 will
be
a. C3H
b. EAH
c. DCH
d. 69H

10. After execution of line 7 of the program, the status of the CY and Z flags will be ….. respectively.
a. 0, 0
b. 0, 1
c. 1, 0
d. 1, 1

Solution (9 & 10): https://www.youtube.com/watch?v=ptzzYWh5DPw

Statement for linked answer questions 11 & 12:
In the Digital to analog converter circuit shown in the figure below, V_R = 10 volts and R = 10 kΩ.

11. The current i is
a. 31.25 µA
b. 62.5 µA
c. 125 µA
d. 250 µA

12. The voltage V_o is
a. – 0.781 volts
b. – 1.562 volts
c. – 3.125 volts
d. – 6.250 volts

Solution (11 & 12) : https://www.youtube.com/watch?v=ByhKwkrj-qs

GATE 2007 ECE Video Solutions on EDC (Electronic Devices and Circuits)

1. The electron and hole concentrations in an intrinsic semiconductor are n_i per cm³ at 300^oK. Now if acceptor impurities are introduced with a concentration of N_A per cm³ (where N_A > n_i), then electron concentration per cm³ at 300^oK will be
a. n_i
b. n_i + N_A
c. N_A – n_i
d. n_i² / NA

Solution : https://www.youtube.com/watch?v=gwb5IZFKDw0

2. In a P⁺N junction diode under reverse bias, the magnitude of electric field is maximum at
a. The edge of the depletion region on P side
b. The edge of the depletion region on N side
c. The P⁺N junction
d. The center of the depletion region on the N side

Solution : https://www.youtube.com/watch?v=986MG7ote5w

3. The correct full wave rectifier circuit is :

Solution : https://www.youtube.com/watch?v=qzbqzCNqYSA

4. A P⁺N junction has a built in potential of 0.8 volts. The depletion layer width at a reverse bias of 1.2 volts is 2 µm. For a reverse bias of 7.2 volts, the depletion layer width will be
a. 4 µm
b. 4.9µm
c. 8 µm
d. 12 µm

Solution : https://www.youtube.com/watch?v=YhbWy1waleM

5. Group I lists four types of PN junction diodes. Match each device in Group I with one of the option in Group II to indicate the bias condition of that device in its normal mode of operation.

Solution : https://www.youtube.com/watch?v=4KUze2mrsoo

6. The DC current gain (β) of a BJT is 50. Assuming that the emitter injection efficiency is 0.995, the base transport factor is:
a. 0.980
b. 0.985
c. 0.990
d. 0.995

Solution : https://www.youtube.com/watch?v=VlsDefl-uG0

7. Group I lists four different semiconductor devices. Match each device in Group I with its characteristic property in Group II.

Solution : https://www.youtube.com/watch?v=iwERJKn2hUU

8. For the BJT circuit shown, assume that the β of the transistor is very large and V_BE is 0.7 volts. The mode of operation of the BJT is

a. Cut off
b. Saturation
c. Normal active
d. Inverse active

Solution : https://www.youtube.com/watch?v=iXf86EM2YOM

9. In the CMOS inverter circuit shown, if the Transconductance parameters of the NMOS and PMOS transistors are K_n = K_p = µ_nC_ox(W_n/L_n) = µ_pC_ox(W_p/L_p) = 40 µA/V² and their threshold voltages are V_Tn = |V_Tp| = 1 volt, the current I is

a. 0 Amp
b. 25 µA
c. 45 µA
d. 90 µA

Solution : https://www.youtube.com/watch?v=wtboLpHXLOA

10. For the zener diode shown in the figure, the zener voltage at knee is 7 volts, the knee current is negligible and the zener dynamic resistance is 10 Ω. If the input voltage (V_i) range is 10 to 16 volts, the output voltage (V_o) ranges from

Solution : https://www.youtube.com/watch?v=CJ5VHPaFMsg

11. The figure shows the high frequency capacitance – voltage (C – V) characteristics of MOS capacitor having an area of 1x10^-4 cm². Assume that the permittivity of silicon and S_iO₂ are 1x10^-12 and 3.5x10^-13 F/cm respectively.

i. The gate oxide thickness in the MOS capacitor is
a. 50 nm
b. 143 nm
c. 350 nm
d. 1 µm

ii. The maximum depletion layer width in silicon is
a. 0.143 µm
b. 0.857 µm
c. 1 µm
d. 1.143 µm

iii. Consider the following statements about the C – V characteristics plot :
S₁: The MOS capacitor has an N type substrate
S₂: If the positive charges are introduced in the oxide, the C – V plot will shift to the left.
Then which one of the following is TRUE .

Solution : https://www.youtube.com/watch?v=IKyIj6hVTL8

GATE 2007 ECE Network Theory - Complete Video Solutions with Answers

GATE 2007 ECE Control Systems - Complete Video Solutions with Answers

GATE 2007 ECE Video Solutions on Analog Circuits (Analog Electronics)

GATE 2007 ECE Video Solution on Digital Circuits (Digital Electronics)

GATE 2007 ECE Video Solutions on EDC (Electronic Devices and Circuits)

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