1. The subtraction of a binary number Y from another binary number X, done by adding 2’s compliment of Y to X, results in a binary number without overflow. This implies that the result is
a. Negative and is in normal form
b. Negative an is in 2’s compliment form
c. Positive and is in normal form
d. Positive and is in 2’s compliment form
Solution :
https://www.youtube.com/watch?v=SMBnnJJrDDE
2. Choose the correct statements relating to the circuit of figure shown
Solution :
https://www.youtube.com/watch?v=zryK-Yl3-Dg
3. A ripple counter using negative edge triggered D flip-flops is shown below. The flip-flops are cleared to ‘0’ at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is :
Solution :
https://www.youtube.com/watch?v=qljzFR3B6TM
4. Fill in the blanks of the statements below concerning the following logic families :
Standard TTL (74XXLL)
Low Power TTL (74LXX)
Low Power Schottky TTL (74LSXX)
Schottky TTL (74SXX)
Emitter Coupled Logic (ECL)
CMOS logic
a. Among the TTL families, …………. Family requires considerably less power than the standard TTL and also has comparable propagation delay.
b. Only the …………… family can operate over a wide range of power supply voltages.
Solution :
https://www.youtube.com/watch?v=jPrNVnV0ZCA
5. For a logic family, given that
VOH is the minimum output high level voltage.
VOL is the maximum output low level voltage.
VIH is the minimum acceptable input low level voltage.
VIL is the maximum acceptable input low level voltage.
Then the correct relationship is
a. VIH>VOH>VIL>VOL
b. VOH > VIH > VIL > VOL
c. VIH > VOH > VOL > VIL
d. VOH > VIH > VOL > VIL
Solution :
https://www.youtube.com/watch?v=nQ473i9xpF8
a. Negative and is in normal form
b. Negative an is in 2’s compliment form
c. Positive and is in normal form
d. Positive and is in 2’s compliment form
2. Choose the correct statements relating to the circuit of figure shown
3. A ripple counter using negative edge triggered D flip-flops is shown below. The flip-flops are cleared to ‘0’ at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is :
4. Fill in the blanks of the statements below concerning the following logic families :
Standard TTL (74XXLL)
Low Power TTL (74LXX)
Low Power Schottky TTL (74LSXX)
Schottky TTL (74SXX)
Emitter Coupled Logic (ECL)
CMOS logic
a. Among the TTL families, …………. Family requires considerably less power than the standard TTL and also has comparable propagation delay.
b. Only the …………… family can operate over a wide range of power supply voltages.
5. For a logic family, given that
VOH is the minimum output high level voltage.
VOL is the maximum output low level voltage.
VIH is the minimum acceptable input low level voltage.
VIL is the maximum acceptable input low level voltage.
Then the correct relationship is
a. VIH>VOH>VIL>VOL
b. VOH > VIH > VIL > VOL
c. VIH > VOH > VOL > VIL
d. VOH > VIH > VOL > VIL
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