GATE 2002 ECE Video Solutions on Analog Circuits (Analog Electronics)

1. In a negative feedback amplifier using voltage-series (Voltage sampling and series mixing) feedback,
a. R_i decreases and R_o decreases
b. R_i decreases and R_o increases
c. R_i increases and R_o decreases
d. R_i increases and R_o increases

Answer: C

Solution: https://www.youtube.com/watch?v=_22d9h7qEFU


2. A 741 OP-AMP has a gain-bandwidth product of 1 MHz. A non-inverting amplifier using this OP-AMP and having a voltage gain of 20 dB will exhibit a –3 dB bandwidth of
a. 50 kHz
b. 100 kHz
c. 100/17 kHz
d. 1000/7.07 kHz

Answer: B

Solution: https://www.youtube.com/watch?v=jg0FBlbWzMU


3. Three identical RC coupled transistor amplifiers are cascaded. If each of the amplifiers has a frequency response as shown in the figure, the overall frequency response is as given in

Answer: A

Solution: https://www.youtube.com/watch?v=EtdsNaauT8g


4. The circuit in the figure employs positive feedback and is intended to generate sinusoidal oscillations. If at a frequency f_o, β(f) = V_f(f)/V_o(f) = 1/6 ∟0^o, then to sustain oscillations at this frequency

a. R₂ = 6R₁
b. R₂ = 5R₁
c. R₂ = R₁/6
d. R₂ = R₁/5

Answer: B

Solution: https://www.youtube.com/watch?v=E28FKsiD0cQ


5. An amplifier using an OP-AMP with a slew rate SR = 1 V/µsec has a gain of 40 dB. If this amplifier has to faithfully amplify sinusoidal signals form dc to 20 kHz without any slew rate induced distortion, then the input signal level must not exceed
a. 795 mV
b. 395 mV
c. 79.5 mV
d. 39.5 mV

Answer: C

Solution: https://www.youtube.com/watch?v=vG62ly43ziE


6. The voltage gain A_v = V_o/V_i of the JFET amplifier shown in the figure is I_DSS = 10 mA, V_P = 5 volts. Assume C₁, C₂ and C_s to be very large.

a. + 16
b. – 16
c. + 8
d. – 6

Answer: D

Solution: https://www.youtube.com/watch?v=9K_U1BcpZSI


7. A triangular voltage waveform V_i(t) is applied at the input to the circuit shown. Assume the diodes to be ideal.

a. Determine the output V_o(t)
b. Neatly sketch the output waveform superimposed on the input V_i(t) and label the key points.

Solution: https://www.youtube.com/watch?v=DwkF8O6Xlvw


8. Below figure shown is a 2 – stage amplifier.

The transistors Q₁ and Q₂ are identical with current gain β = 100, further β_DC = β_ac = β. The zener diode D_z has a break down region and its dynamic resistance r_z is zero. The capacitors C₁ and C₂ are large and provide negligible impedance at signal frequencies.
a. Identify the configuration in each of the amplifier stages. (i.e. whether CE, CC or CB)
b. Determine the quiescent quantities of I_C1 and V_C1.
c. Determine an expression for the voltage gain V_o/V_s and determine its value. (Assume V_BE = 0.7 volts, r_o = ∞ and thermal voltage V_T = 25mV)
Answer:
Solution:


9. Consider the circuit shown. Assume the operational amplifier is ideal.

a. In which mode is the BJT operating (active or saturation or cutoff)? Justify your answer.
b. Obtain an expression relating the output current I_o and the input voltage V_i.
c. Determine Io and V_op if V_i = 2 volt. Assume β = 99 and V_BE = 0.7 volts.

Answer:
(a) Active region
(b) V_i = I_OR_L – 15
(c) I_O = 1.7 Amp, V_OP = 5.25 volts

Solution: https://www.youtube.com/watch?v=F4ZuatGRJO0

GATE 2002 ECE Video Solution on Digital Circuits (Digital Electronics)

1. 4 – bit 2’s complement representation of a decimal number is 1000. The number is
a. +8
b. 0
c. -7
d. -8

Answer:D

Solution : https://www.youtube.com/watch?v=cZVj5TPGuWo


2. If the input to the digital circuit of the figure, consisting of a cascade of 20 XOR gates is X, then the output Y is equal to

Answer:B

Solution : https://www.youtube.com/watch?v=iRCfbhzqgOQ


3. The number of comparators required in a 3 bit comparator type ADC is
a. 2
b. 3
c. 7
d. 8

Answer:C

Solution : https://www.youtube.com/watch?v=ewhv3AAXJHY


4. The gates G₁ and G₂ in the figure is have propagation delays of 10 ns and 20 ns respectively. If the input V_i makes an abrupt change from logic 0 to 1 at time t = t_o, then the output waveform V_o is

Answer:B

Solution : https://www.youtube.com/watch?v=1OBRbAVQ43E


5. The circuit in the figure is ahs two CMOS NOR gates. This circuit functions as a

a. Flip-flop
b. Schmitt trigger
c. Monostable multivibrator
d. Astable multivibrator

Answer:C

Solution : https://www.youtube.com/watch?v=e8-iK3AGuRY


6. If the inputs X₃, X₂, X₁, X₀ to the ROM in the figure are 8-4-2-1 BCD numbers, then the outputs Y₃Y₂Y₁Y₀ are

a. Gary code numbers
b. 2-4-2-1 BCD numbers
c. Excess-3 code numbers
d. None of the above

Answer:B

Solution : https://www.youtube.com/watch?v=kzMI2giuNT0


7. Consider the following assembly language program.
MVI B, 87H
MOV A, B
START: JMP NEXT
MVI B, 00H
XRA B
OUT PORT1
HLT
NEXT: XRA B
JP START
OUT PORT2
HLT
The execution of the above program in an 8085 microprocessor will result in
a. An output of 87H at PORT1
b. An output of 87H at PORT2
c. Infinite looping of the program execution with accumulator data remaining at 00H
d. Infinite looping of the program execution with accumulator data alternating between 00H and 87H

Answer:B

Solution : https://www.youtube.com/watch?v=3Z_LU8RWke0


8. The inputs to a digital circuit shown in figure is are the external signals A, B and C. Assume complements of A, B and C are not available. The +5 volts power supply (logic 1) and the ground (logic 0) are also available.

a. Write down the output function in its canonical SOP and POS forms.
b. Implement the circuit using only 2 to 1 multiplexers shown in the figure, where S is the data select line, D₀ and D₁ are the input data lines and Y is the output line. The function table is also given for the multiplexer.

Solution : https://www.youtube.com/watch?v=IVwb-z4V3x0


9. It is required to design a binary mod-5 synchronous counter using AB flip-flop, such that the output Q₂Q₁Q₀ changes as 000 -> 001 -> 010..... and so on. The truth table for the AB flip-flop is given in figure.

a. Write down the state table for the mod-5 counter
b. Obtain simplified SOP expressions for the inputs A₂, B₂, A₁, B₁, A₀ and B₀ in terms of Q₂, Q₁, Q₀ and their complements.
c. Hence complete the circuit diagram for the mod-5 counter given in the figure using minimum number of 2 input NAND gate only.

Solution : https://www.youtube.com/watch?v=2HJzJK-C38Y


10. An 8085 microprocessor operating at 5 MHz clock frequency executes the following routine.
START: MOV A, B
OUT 55H
DCR B
STA FFF8H
JNP START
a. Determine the total number of machine cycles required to execute the routine till the JMP instruction is executed for the first time.
b. Determine the time interval between two consecutive (MEMW)’ signals.
c. If the external logic controls the READSY line so that three WAIT states are introduced in the I/O WRITE machine cycle, determine the time interval between two consecutive (MEMW)’ signals.

Solution :

GATE 2002 ECE Video Solutions on EDC (Electronic Devices and Circuits)

1. In the figure shown, a silicon diode is carrying a constant current of 1 mA. When the temperature of the diode is 20^oC, diode voltage is found to be 700 mV. If the temperature rises to 40^oC, diode voltage becomes approximately equal to

a. 740 mV
b. 660 mV
c. 680 mV
d. 700 mV

Answer: B

Solution : https://www.youtube.com/watch?v=wqUUbrQy-CI


2. If the transistor in figure is in saturation, then

Answer: D

Solution : https://www.youtube.com/watch?v=eGQmSi1Xdxk



3. A zener diode regulator in figure, is to be designed to meet the specifications : I_L = 10 mA, V_o = 10 volts and V_in varies from 30 to 50 volts. The zener diode has V_Z = 10 volts and I_ZK (knee current) = 1 mA. For satisfactory operation

Answer: A

Solution : https://www.youtube.com/watch?v=OCR60jVExa4



4. Consider the following statements in connection with the CMOS inverter in figure, where both the MOSFETs are of enhancement type and both have a threshold voltage of 2 volts.

S₁: T₁ conducts when V_I ≥ 2 volts.
S₂: T₁ is always in saturation when V_o = 0 volts.
Which of the following is correct.
a. Only S₁ is TRUE
b. Only S₂ is TRUE
c. Both are TRUE
d. Both are FALSE

Answer: A

Solution : https://www.youtube.com/watch?v=lm9CG4kv7NU



5. Each transistor in figure, has a dc current gain β_dc = 50, cut in voltage V_γ = 0.65 volts and V_BEsat = 0.75 volts. The output voltage V_o for T₂ in saturation can be as high as 0.2 volts. Assume 0.7 volts drop across a conducting PN junction.

Determine
(a) The minimum value I_B2 necessary to keep T₂ saturation.
(b) The maximum permissible value for the resistance R_B1.
(c) The worst case high input (logic 1) and the worst case low input (logic 0)
for which T₂ will be either in saturation or in cut off.

Answer: (a) 96 µA (b) 14.5 kΩ (c) 2.1 volts and 1.35 volts

Solution : https://www.youtube.com/watch?v=J4uyyFXmVM4