Set – 1 (15th February 2014 (Forenoon))
1. In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 volt. Ignoring the body effect, the output voltages at P, Q, and R are
Solution : https://www.youtube.com/watch?v=GPvxbZy6dVA
2. The Boolean expression simplifies to
Solution : https://www.youtube.com/watch?v=YyIX-T6Bsi0
3. Five JK flip flops are cascaded to form the circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in KHz) of the waveform at Q3 is …………
Solution : https://www.youtube.com/watch?v=ID70DQCpDCg
4. The output F in the digital logic circuit shown in the figure is
Solution : https://www.youtube.com/watch?v=cIpdKO6C078
5. For the given Boolean function, which one of the following is the complete set of essential prime implicants?
Solution : https://www.youtube.com/watch?v=tGOgs59wtFc
6. The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate. Suppose the XOR gate is replaced by the XNOR gate. Which one of the following options preserves the state diagram?
Solution : https://www.youtube.com/watch?v=tBqtKpt1oSE
SET – 2 (15th February 2014 (Afternoon))
1. For an n – variable Boolean function, the maximum number of prime implicants is
a. 2(n – 1)
b. n/2
c. 2n
d. 2(n – 1)
Solution : https://www.youtube.com/watch?v=wBQo_GVTK58
2. The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is ………….
Solution : https://www.youtube.com/watch?v=xAqo_3bT9fI
3. In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X – Y) are given by
Solution : https://www.youtube.com/watch?v=dZblXWcOBkY
4. In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.
a. W1
b. W2
c. W3
d. W4
Solution : https://www.youtube.com/watch?v=E3XeZjGgzqY
5. The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is
a. 01110….
b. 01010…..
c. 00110….
d. 01100…..
Solution : https://www.youtube.com/watch?v=wNoctGWwcfs
6. For the 8085 microprocessor, the interfacing circuit to input 8 – bit digital data (DI0 – DI7) from an external device is shown in figure. The instruction for correct data transfer is
a. MVI A, F8H
b. IN F8H
c. OUT F8H
d. LDA F8F8H
Solution : https://www.youtube.com/watch?v=IH6ybT3DsAs
SET – 3 (16th February 2014 (Forenoon))
1. An analog voltage in the range 0 to 8 volts is divided in 16 equal intervals for conversion to 4 – bit digital output. The maximum quantization error (in volts) is ………..
Solution : https://www.youtube.com/watch?v=cH9U89uQWog
2. The circuit shown in the figure is a
a. Toggle flip flop
b. JK flip flop
c. SR Latch
d. Master – Slave D flip flop
Solution : https://www.youtube.com/watch?v=AvKzOVpre_k
3. Consider the multiplexer based logic circuit shown in the figure.
Solution : https://www.youtube.com/watch?v=UCXcNdwJCE0
4. If WL is the Word Line and BL is the Bit Line, an SRAM cell is shown is
Solution : https://www.youtube.com/watch?v=x_loyq03c4k
5. In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by
Solution : https://www.youtube.com/watch?v=QUrG-AIkZ4g
6. If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?
Solution : https://www.youtube.com/watch?v=Y2hhJ5DqloE
SET - 4 (16th February 2014 (Afternoon))
1. For a given sample and hold circuit, if the value of the hold capacitor is increased, then
a. Droop rate decreases and Acquisition time decreases
b. Droop rate decreases and Acquisition time increases
c. Droop rate increases and Acquisition time decreases
d. Droop rate increases and Acquisition time increases
Solution : https://www.youtube.com/watch?v=hdo5X7vDKuc
2. In the circuit shown in the figure, if C = 0, the expression for Y is
Solution : https://www.youtube.com/watch?v=zVTaxNYq03A
3. The output (Y) of the circuit shown in the figure is
Solution : https://www.youtube.com/watch?v=l2fIDfULTkQ
4. An 8 – to – 1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by
Solution : https://www.youtube.com/watch?v=lzyFivtrX6o
5. A 16 bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry propagation delay of each FA is 12 ns and the sum propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16 – bit adder will be…………
Solution : https://www.youtube.com/watch?v=jVNqRmlWhaU
6. An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the accumulator to the 16 bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A15 - A8 is
Solution : https://www.youtube.com/watch?v=RrlGPv7adtU
1. In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 volt. Ignoring the body effect, the output voltages at P, Q, and R are
2. The Boolean expression simplifies to
3. Five JK flip flops are cascaded to form the circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in KHz) of the waveform at Q3 is …………
4. The output F in the digital logic circuit shown in the figure is
5. For the given Boolean function, which one of the following is the complete set of essential prime implicants?
6. The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate. Suppose the XOR gate is replaced by the XNOR gate. Which one of the following options preserves the state diagram?
SET – 2 (15th February 2014 (Afternoon))
1. For an n – variable Boolean function, the maximum number of prime implicants is
a. 2(n – 1)
b. n/2
c. 2n
d. 2(n – 1)
2. The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is ………….
3. In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X – Y) are given by
4. In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.
a. W1
b. W2
c. W3
d. W4
5. The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is
a. 01110….
b. 01010…..
c. 00110….
d. 01100…..
6. For the 8085 microprocessor, the interfacing circuit to input 8 – bit digital data (DI0 – DI7) from an external device is shown in figure. The instruction for correct data transfer is
a. MVI A, F8H
b. IN F8H
c. OUT F8H
d. LDA F8F8H
SET – 3 (16th February 2014 (Forenoon))
1. An analog voltage in the range 0 to 8 volts is divided in 16 equal intervals for conversion to 4 – bit digital output. The maximum quantization error (in volts) is ………..
2. The circuit shown in the figure is a
a. Toggle flip flop
b. JK flip flop
c. SR Latch
d. Master – Slave D flip flop
3. Consider the multiplexer based logic circuit shown in the figure.
4. If WL is the Word Line and BL is the Bit Line, an SRAM cell is shown is
5. In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by
6. If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?
SET - 4 (16th February 2014 (Afternoon))
1. For a given sample and hold circuit, if the value of the hold capacitor is increased, then
a. Droop rate decreases and Acquisition time decreases
b. Droop rate decreases and Acquisition time increases
c. Droop rate increases and Acquisition time decreases
d. Droop rate increases and Acquisition time increases
2. In the circuit shown in the figure, if C = 0, the expression for Y is
3. The output (Y) of the circuit shown in the figure is
4. An 8 – to – 1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by
5. A 16 bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry propagation delay of each FA is 12 ns and the sum propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16 – bit adder will be…………
6. An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the accumulator to the 16 bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A15 - A8 is
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