1. Each cell of a Static Random Access Memory contains
a. 6 MOS transistors
b. 4 MOS transistors and 2 capacitors
c. 2 MOS transistors and 4 capacitors
d. 1 MOS transistor and 1 capacitor
Solution : https://www.youtube.com/watch?v=czmSOocbEuY
2. A two bit binary multiplier can be implemented using
a. 2 input AND gates only
b. 2 input XOR gates and 2 input AND gates only
c. Two 2 input NOR gates and one XOR gate
d. XOR gates and shift registers
Solution : https://www.youtube.com/watch?v=lhcgCBSXH80
3. In standard TTL, the ‘Totem pole’ stage refers to
a. Multi emitter input stage
b. Phase splitter
c. Output buffer
d. Open collector output stage
Solution : https://www.youtube.com/watch?v=vwfJMmfEvMQ
4. The inverter 74ALS04 has the following specifications:
IOHmax = -0.4 mA
IOLmax = 8 mA
IIHmax = 20 µA
IILmax = -0.1 mA
The fan out based on the above will be
a. 10
b. 20
c. 60
d. 100
Solution : https://www.youtube.com/watch?v=Yp9f6sedeGc
5. The output of the logic gate shown is
a. 0
b. 1
c. A
d. A’
Solution : https://www.youtube.com/watch?v=k8wTh4Irumg
6. In 8085 µP system, the RST instruction will cause an interrupt
a. Only if an interrupt service routine is not being executed
b. Only if a bit in the interrupt mask is made 0
c. Only if interrupts have been enabled by an EI instruction
d. None of the above
Answer:
Solution :
7. The decoding circuit is shown in figure, has been used to generated the active low chip select signal for a microprocessor peripheral (The address lines are designated as A0 to A7 for I/O addresses).
a. 60H – 63H
b. A4 – A7H
c. 30 – 33H
d. 70 – 73H
Solution : https://www.youtube.com/watch?v=lMANeBdPfyg
8. In a JK flip flop, we have J = Q’ and K = 1. Assume the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be
a. 010000
b. 011001
c. 010010
d. 010101
Solution : https://www.youtube.com/watch?v=xLkAhzePI90
9. For the NMOS logic gate shown, the logic function implemented is
Solution : https://www.youtube.com/watch?v=PEBwvZKpr_c
10. The Boolean function A + BC is a reduced form of
a. AB + BC
b. (A + B)(A + C)
c. A’B + AB’C
d. (A + C)B
Solution : https://www.youtube.com/watch?v=R64pdVEnmxI
11. The following instructions have been executed by an 8085 µP
For which address will the next instruction be fetched?
a. 6019
b. 6379
c. 6979
d. None of the above
Answer:
Solution :
12. A signed integer has been stored in a byte using the 2’s complement format. We wish to store the same integer in a 16 bit word. We should
a. copy the original byte to the less significant byte of the word and fill the more significant with zeros
b. copy the original byte to the more significant byte of the word and fill the less significant with zeros
c. copy the original byte to the less significant byte of the word and make fit of the more significant byte equal to the most significant bit of the original byte
d.copy the original byte to the less significant byte of the word as well as the more significant byte of the word
Solution : https://www.youtube.com/watch?v=KPDGRwll9LE
13. Match the following :
Solution : https://www.youtube.com/watch?v=LrV0a_yBGng
14. Match the following, while moving data between registers of the 8085 and the stack
Answer:
Solution :
15. Circuit shown in the figure is an NMOS shift register. All transistors are NMOS enhancement type with threshold voltage VT = 1 volt. Supply used is VDD = 5 volts.
Two non- overlapping clocks ø1 and ø2 are as shown in the figure is and have large pulse widths.
All capacitors are initially discharged and the Vin = 0 volts is applied. If values of capacitors are C1 = 2 pF and C2 = 1 pF. Find out voltage VC2 on capacitor C2 after ø2 goes low. Neglect body effect on VT in your evaluation.
Solution : https://www.youtube.com/watch?v=fa7OqcOcap0
16. A sequence generator is shown in figure. The counter status (Q0Q1Q2) is initialized to 010 using preset/clear inputs.
The clock has a period of 50 ns and transitions take place at the rising clock edge.
a. Give the sequence generates a tQ0 till repeats.
b. What is the repetition rate of the generated sequence?
Solution : https://www.youtube.com/watch?v=iOk6-PX-kY8
17. An 8085 µP uses a 2 MHz crystal. Find the time taken by it to execute the following delay subroutine, inclusive of the call instruction in the calling program.
You are given that a CALL instruction takes 18 cycles of the system clock, PUSH requires 12 cycles and conditional jump takes 10 cycles if the jump is taken and 7 cycles if it is not. All other instructions used above take (3n + 1) clock cycles, where n is the number of accesses to the memory, inclusive of the opcode fetch.
Solution :
a. 6 MOS transistors
b. 4 MOS transistors and 2 capacitors
c. 2 MOS transistors and 4 capacitors
d. 1 MOS transistor and 1 capacitor
2. A two bit binary multiplier can be implemented using
a. 2 input AND gates only
b. 2 input XOR gates and 2 input AND gates only
c. Two 2 input NOR gates and one XOR gate
d. XOR gates and shift registers
3. In standard TTL, the ‘Totem pole’ stage refers to
a. Multi emitter input stage
b. Phase splitter
c. Output buffer
d. Open collector output stage
4. The inverter 74ALS04 has the following specifications:
IOHmax = -0.4 mA
IOLmax = 8 mA
IIHmax = 20 µA
IILmax = -0.1 mA
The fan out based on the above will be
a. 10
b. 20
c. 60
d. 100
5. The output of the logic gate shown is
a. 0
b. 1
c. A
d. A’
6. In 8085 µP system, the RST instruction will cause an interrupt
a. Only if an interrupt service routine is not being executed
b. Only if a bit in the interrupt mask is made 0
c. Only if interrupts have been enabled by an EI instruction
d. None of the above
Answer:
Solution :
7. The decoding circuit is shown in figure, has been used to generated the active low chip select signal for a microprocessor peripheral (The address lines are designated as A0 to A7 for I/O addresses).
a. 60H – 63H
b. A4 – A7H
c. 30 – 33H
d. 70 – 73H
8. In a JK flip flop, we have J = Q’ and K = 1. Assume the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be
a. 010000
b. 011001
c. 010010
d. 010101
9. For the NMOS logic gate shown, the logic function implemented is
10. The Boolean function A + BC is a reduced form of
a. AB + BC
b. (A + B)(A + C)
c. A’B + AB’C
d. (A + C)B
11. The following instructions have been executed by an 8085 µP
For which address will the next instruction be fetched?
a. 6019
b. 6379
c. 6979
d. None of the above
Answer:
Solution :
12. A signed integer has been stored in a byte using the 2’s complement format. We wish to store the same integer in a 16 bit word. We should
a. copy the original byte to the less significant byte of the word and fill the more significant with zeros
b. copy the original byte to the more significant byte of the word and fill the less significant with zeros
c. copy the original byte to the less significant byte of the word and make fit of the more significant byte equal to the most significant bit of the original byte
d.copy the original byte to the less significant byte of the word as well as the more significant byte of the word
13. Match the following :
14. Match the following, while moving data between registers of the 8085 and the stack
Answer:
Solution :
15. Circuit shown in the figure is an NMOS shift register. All transistors are NMOS enhancement type with threshold voltage VT = 1 volt. Supply used is VDD = 5 volts.
Two non- overlapping clocks ø1 and ø2 are as shown in the figure is and have large pulse widths.
All capacitors are initially discharged and the Vin = 0 volts is applied. If values of capacitors are C1 = 2 pF and C2 = 1 pF. Find out voltage VC2 on capacitor C2 after ø2 goes low. Neglect body effect on VT in your evaluation.
Solution : https://www.youtube.com/watch?v=fa7OqcOcap0
16. A sequence generator is shown in figure. The counter status (Q0Q1Q2) is initialized to 010 using preset/clear inputs.
The clock has a period of 50 ns and transitions take place at the rising clock edge.
a. Give the sequence generates a tQ0 till repeats.
b. What is the repetition rate of the generated sequence?
Solution : https://www.youtube.com/watch?v=iOk6-PX-kY8
17. An 8085 µP uses a 2 MHz crystal. Find the time taken by it to execute the following delay subroutine, inclusive of the call instruction in the calling program.
You are given that a CALL instruction takes 18 cycles of the system clock, PUSH requires 12 cycles and conditional jump takes 10 cycles if the jump is taken and 7 cycles if it is not. All other instructions used above take (3n + 1) clock cycles, where n is the number of accesses to the memory, inclusive of the opcode fetch.
Solution :
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50 stored in memory starting at address F300H 1-Find out how many unsigned 16-bit numbers with 4444H values by drawing the flow diagram, Design, and briefly explain the working principle. Program 6802 It will be in the form of a translator resource file, in the language of the microprocessor All necessary definitions and descriptions of each line of the command. Please write with an explanation.
ReplyDelete2- You can download the program in the dialer with the starting address of F200H. Compile it to obtain the output file. Using a simulator program analysis in table form on the affected registers and memory eyes. Do it by showing the step-by-step work. Total work of the program Find the time with the simulator and write it.
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