1991
1. Two dimensional addressing of 256 X 8 bit ROM using 8 to 1
selectors requires _______ (how many?) NAND gates.
Answer: 2304
Solution : https://www.youtube.com/watch?v=6TdeOmgMTvs
2. The CMOS equivalent of the following nMOS gate (shown in
figure) is ________ (Draw the circuit).
Answer: (A + BC)'
Solution : https://www.youtube.com/watch?v=9cSuZt-UrPo
3. A bit stored in a FAMOS device can be erased by ___________.
Answer: UV Light
Solution : https://www.youtube.com/watch?v=mwBl4KpMcLs
4. In the figure, the Boolean expression for the output in
terms of inputs A, B and C when the clock CK is high, is given by ____________
Answer: (A + B)C
Solution : https://www.youtube.com/watch?v=cbPlHJk9zNA
1992
1. Choose the correct statement(s) from the following:
a.
PROM contains a programmable AND
array and a fixed OR array
b.
PLA contains a fixed AND array and a
programmable OR array
c.
PROM contains a fixed AND array and
a programmable OR array
d.
PLA contains a programmable AND
array and a programmable OR array
Answer: C & D
Solution : https://www.youtube.com/watch?v=z2tByyE5L24
1993
1.
A microprocessor has five address lines [A4
– A0] and eight data lines [D7 – D0]. An input
device A, an output device B, a ROM and a RAM are memory mapped to the
microprocessor at the addresses as shown in figure. Devices A and B have four
addressable registers each/ RAM has 8 bytes and ROM has 16 bytes.
a.
Indicate the address lines to be
connected to each device and memory.
b.
Obtain the minimum sum of product
expression for the chip select (CS) function of each device/memory.
Solution
: https://www.youtube.com/watch?v=-WfheT4XoTI
1994
1. A PLA can be used
a.
As a microprocessor
b.
As a dynamic memory
c.
To realize a sequential logic
d.
To realize a combinational logic
Answer: D
Solution : https://www.youtube.com/watch?v=fYhAnr1GAf4
2. A dynamic RAM consists of
a.
6 transistors
b.
2 transistors and 2 capacitors
c.
1 transistor and 1 capacitor
d.
2 capacitors only
Answer: C
Solution : https://www.youtube.com/watch?v=3ES3fiMXozE
3. A 2 µsec
pulse can be stretched into a 10 msec pulse by using a _______ circuit.
Answer: Mono Stable Multivibrator
Solution : https://www.youtube.com/watch?v=SHa-rhT0da0
1995
1. The minimum number of MOS transistors required to make a
dynamic RAM cell is
a.
1
b.
2
c.
3
d.
4
Answer: A
Solution : https://www.youtube.com/watch?v=0zh1pqRqIPY
2. A ROM is used to implement the Boolean functions given
below.
a.
What is the minimum size of the ROM
required?
b.
Determine the data in each location
of the ROM
Solution : https://www.youtube.com/watch?v=kqnpFRi_gYQ
1996
1. A Dynamic RAM cell which holds 5 volts has to be refreshed
every 20 ms, so that the stored voltage does not fall by more than 0.5 volts.
If the cell has a constant discharge current of 0.1 pA, the storage capacitance
of the cell is
a.
4 x 10-5 Farads
b.
4 x 10-9 Farads
c.
4 x 10-12 Farads
d.
4 x 10-15 Farads
Answer:D
2. A memory system of size 26K bytes is required to be designed
using memory chips which have 12 address lines and 4 data lines each. The
number of such chips required to design the memory system is
a.
2
b.
4
c.
8
d.
13
Answer:D
3. It is desired to generate the following three Boolean
functions using an OR array as shown in figure, where P1 to P5
are the product terms in one or more of the variables a, a’, b, b’, c and
c’.
Write down the terms P1,
P2, P3, P4 and P5.
1997
1. Each cell of a Static Random Access Memory contains
a.
6 MOS transistors
b.
4 MOS transistors and 2 capacitors
c.
2 MOS transistors and 4 capacitors
d.
1 MOS transistor and 1 capacitor
2. For the NMOS logic gate shown, the logic function
implemented is
3. Match the following :
2000
1. For the CMOS monostable multivibrator of given figure, R =
50 KΩ and C = 0.01 µF, VDD = 5 volts, and the CMOS NOR gates have a
threshold voltage (VT) of 1.5 volts. Vin is a trigger
pulse (Ï„p << RC) as shown in the figure.
a.
Plot VA1 and Vo1
as functions of time.
b.
Write the equation for VR(t),
for t > 0
c.
Find the time period of the output
pulse.
2001
1. An 8085 microprocessor based system uses a 4K x8 bit RAM
whose starting address is AA00H. The address of the last byte in this RAM is
a.
0FFFH
b.
1000H
c.
B9FFH
d.
BA00H
Answer: C
2. In the DRAM cell in the figure is the VT of the
N-MOSFET is 1 volt. For the following three combinations of WL and BL voltages.
a.
5V; 3V; 7V
b.
4V; 3V; 4V
c.
5V; 5V; 5V
d.
4V; 4V; 4V
Answer: B
2002
1. The circuit in the figure is ahs two CMOS NOR gates. This
circuit functions as a
a.
Flip-flop
b.
Schmitt trigger
c.
Monostable multivibrator
d.
Astable multivibrator
Answer: C
2003
1. In the circuit shown in the figure, ‘A’ is a parallel in,
parallel out 4 bit shift register, which loads at the rising edge of the clock
C. The input lines are connected to a 4 bit bus, W. Its output acts as the
input to a 16 X 4 ROM, whose output is floating when the enable input E is 0.
A partial table of the
contents of the ROM is as follows.
The clock to the register is shown, and the data on the W
bus at time t1 is 0110. The data on the bus at time t2 is
Address
|
0
|
2
|
4
|
6
|
8
|
10
|
11
|
14
|
Data
|
0011
|
1111
|
0100
|
1010
|
1011
|
1000
|
0010
|
1000
|
a.
1111
b.
1011
c.
1000
d.
0010
2005
1. What memory address range is NOT represented by chip #1 and
chip #2 in the figure. A0 to A15 in this figure are the address lines and CS
means chip select.
a.
0100 – 02FF
b.
1500 – 16FF
c.
F900 – FAFF
d.
F800 – F9FF
Answer: D
Solution : https://www.youtube.com/watch?v=bv_jlwR4ivs
2013
1. There are four chips each of 1024 bytes connected to a 16
bit address bus as shown in the figure below. RAMs 1,2,3 and 4 respectively are
mapped to addresses
Answer: D
Solution : https://www.youtube.com/watch?v=BenlPrppZYU
2014
1. In the following circuit employing pass transistor logic,
all NMOS transistors are identical with a threshold voltage of 1 volt. Ignoring
the body effect, the output voltages at P, Q, and R are
Answer: C
2. If WL is the Word Line and BL is the Bit Line, an SRAM cell
is shown is
Answer: B
3. The output (Y) of the circuit shown in the figure is
Answer: A
Thanks for ur detailed explanation and it's very useful for level 0 learners
ReplyDeletenice thank u
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